Yield optimization with energy-delay constraints in low-power digital circuits

Yu Cao; Huifang Qin; Ruth Wang; Paul Friedberg; Andrei Vladimirescu; Jan Rabaey

doi:10.1109/EDSSC.2003.1283533

Yield optimization with energy-delay constraints in low-power digital circuits

Yu Cao, Huifang Qin, Ruth Wang, Paul Friedberg, Andrei Vladimirescu, Jan Rabaey

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Scopus citations

Abstract

As circuit parametric variations aggravate in advanced technology, yield emerges as an important figure-of-merit in circuit design. Based on a 130nm technology, the yield-energy-delay tradeoffs in low-power circuit optimization are investigated. Using a log-normal statistical model, Monte-Carlo analyses are performed on typical circuit examples, including an inverter chain, NAND gate, and 4-bit adder. While energy reduction can be effectively achieved by tuning supply voltage (V_dd), threshold voltage (V_tb), and device width (W), circuit yield degrades during this process. On the other hand, it is observed that performance variability is relatively insensitive to circuit topology and device length (L). Design guidelines for optimizing yield in the presence of parametric variations and energy-delay constraints are proposed.

Original language	English (US)
Title of host publication	2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	285-288
Number of pages	4
ISBN (Electronic)	0780377494, 9780780377493
DOIs	https://doi.org/10.1109/EDSSC.2003.1283533
State	Published - 2003
Externally published	Yes
Event	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 - Tsimshatsui, Kowloon, Hong Kong Duration: Dec 16 2003 → Dec 18 2003

Publication series

Name	2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Conference

Conference	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Country/Territory	Hong Kong
City	Tsimshatsui, Kowloon
Period	12/16/03 → 12/18/03

Bibliographical note

Publisher Copyright:
©2003 IEEE.

Publisher link

10.1109/EDSSC.2003.1283533

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Cao, Y., Qin, H., Wang, R., Friedberg, P., Vladimirescu, A., & Rabaey, J. (2003). Yield optimization with energy-delay constraints in low-power digital circuits. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 (pp. 285-288). Article 1283533 (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2003.1283533

Yield optimization with energy-delay constraints in low-power digital circuits. / Cao, Yu; Qin, Huifang; Wang, Ruth et al.
2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. p. 285-288 1283533 (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Cao, Y, Qin, H, Wang, R, Friedberg, P, Vladimirescu, A & Rabaey, J 2003, Yield optimization with energy-delay constraints in low-power digital circuits. in 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003., 1283533, 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Institute of Electrical and Electronics Engineers Inc., pp. 285-288, IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Tsimshatsui, Kowloon, Hong Kong, 12/16/03. https://doi.org/10.1109/EDSSC.2003.1283533

Cao Y, Qin H, Wang R, Friedberg P, Vladimirescu A, Rabaey J. Yield optimization with energy-delay constraints in low-power digital circuits. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 285-288. 1283533. (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003). doi: 10.1109/EDSSC.2003.1283533

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abstract = "As circuit parametric variations aggravate in advanced technology, yield emerges as an important figure-of-merit in circuit design. Based on a 130nm technology, the yield-energy-delay tradeoffs in low-power circuit optimization are investigated. Using a log-normal statistical model, Monte-Carlo analyses are performed on typical circuit examples, including an inverter chain, NAND gate, and 4-bit adder. While energy reduction can be effectively achieved by tuning supply voltage (Vdd), threshold voltage (Vtb), and device width (W), circuit yield degrades during this process. On the other hand, it is observed that performance variability is relatively insensitive to circuit topology and device length (L). Design guidelines for optimizing yield in the presence of parametric variations and energy-delay constraints are proposed.",

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AB - As circuit parametric variations aggravate in advanced technology, yield emerges as an important figure-of-merit in circuit design. Based on a 130nm technology, the yield-energy-delay tradeoffs in low-power circuit optimization are investigated. Using a log-normal statistical model, Monte-Carlo analyses are performed on typical circuit examples, including an inverter chain, NAND gate, and 4-bit adder. While energy reduction can be effectively achieved by tuning supply voltage (Vdd), threshold voltage (Vtb), and device width (W), circuit yield degrades during this process. On the other hand, it is observed that performance variability is relatively insensitive to circuit topology and device length (L). Design guidelines for optimizing yield in the presence of parametric variations and energy-delay constraints are proposed.

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Yield optimization with energy-delay constraints in low-power digital circuits

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