David E. Krekelberg, Gerald E Sobelman, Chu S. Jhon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations


The authors describe the YASC high-level silicon compiler which synthesizes compact chip layouts from hierarchical behavioral descriptions. A logic synthesis procedure generates sets of Boolean equations, including multiphase clocks and any necessary interface logic. A novel technique for layout generation yields cells whose densities approach hand-crafted designs. Two-layer metal NMOS and CMOS technologies are supported, with flexible design rules. In addition to layout synthesis, logic, schematic and graph diagrams are generated directly from a powerful internal database. The compiler, which runs under the UNIX operating system, includes a menu-driven multiwindowing user environment.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Number of pages7
ISBN (Print)0818606355
StatePublished - Dec 1 1985

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0146-7123


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