Abstract
We evaluate the performance impact of two different write-buffer configurations (one word per buffer entry and one block per buffer entry) and two different write-policies (write-through and write-back), when using the partial block invalidation coherence mechanism [3] in a shared-memory multiprocessor. Using an execution-driven simulator, we find that the one word per entry buffer configuration with a write-back policy is preferred for small write-buffer sizes when both buffers have an equal number of data words, and when they have equal hardware cost. Furthermore, when partial block invalidation is supported, we find that a write-through policy is preferred over a write-back policy due to its simpler cache hit detection mechanisms, its elimination of write-back transactions, and its competitive performance when the write-buffer is relatively large.
Original language | English (US) |
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Pages | 506-511 |
Number of pages | 6 |
State | Published - Dec 1 1995 |
Event | Proceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Austin, TX, USA Duration: Oct 2 1995 → Oct 4 1995 |
Other
Other | Proceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors |
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City | Austin, TX, USA |
Period | 10/2/95 → 10/4/95 |