Write buffer design for cache-coherent shared-memory multiprocessors

Farnaz Mounes-Toussi, David J. Lilja

Research output: Contribution to conferencePaper

3 Scopus citations

Abstract

We evaluate the performance impact of two different write-buffer configurations (one word per buffer entry and one block per buffer entry) and two different write-policies (write-through and write-back), when using the partial block invalidation coherence mechanism [3] in a shared-memory multiprocessor. Using an execution-driven simulator, we find that the one word per entry buffer configuration with a write-back policy is preferred for small write-buffer sizes when both buffers have an equal number of data words, and when they have equal hardware cost. Furthermore, when partial block invalidation is supported, we find that a write-through policy is preferred over a write-back policy due to its simpler cache hit detection mechanisms, its elimination of write-back transactions, and its competitive performance when the write-buffer is relatively large.

Original languageEnglish (US)
Pages506-511
Number of pages6
StatePublished - Dec 1 1995
EventProceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Austin, TX, USA
Duration: Oct 2 1995Oct 4 1995

Other

OtherProceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors
CityAustin, TX, USA
Period10/2/9510/4/95

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    Mounes-Toussi, F., & Lilja, D. J. (1995). Write buffer design for cache-coherent shared-memory multiprocessors. 506-511. Paper presented at Proceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors, Austin, TX, USA, .