Skip to main navigation Skip to search Skip to main content

Wiresizing with buffer placement and sizing for power-delay tradeoffs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fingerprint

Dive into the research topics of 'Wiresizing with buffer placement and sizing for power-delay tradeoffs'. Together they form a unique fingerprint.
Sort by

Computer Science

Engineering

Social Sciences

Keyphrases