Abstract
An efficient solution to the wire sizing problem using the Elmore delay model is proposed. Two formulations of the problem are put forth. In the first, the minimum interconnect delay is sought, while in the latter, we minimize the net delay under delay constraints at the leaf nodes; previous approaches solve only the former problem. Theoretical results on these problems are proved, and two algorithms are presented. One is a sensitivity-based heuristic, vrhile the other is a rigorous convex optimization problem. It is shown experimentally that the sensitivity-based heuristic gives near-optimal results with reasonable runtimes. A smooth area-delay tradeoff is shown, and results are presented to illustrate the fact that sizing for minimum delay is not a good engineering goal. Instead, a delay goal of even 15% over the minimum provides significantly better engineering solutions.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1001-1011 |
| Number of pages | 11 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 15 |
| Issue number | 8 |
| DOIs | |
| State | Published - 1996 |
Bibliographical note
Funding Information:Manuscript received March 25, 1994: revised December 9, 1994 and January 17, 1996. This work was supported in part by the National Science Foundation Faculty Early Career Development Award under Contract MIP-9502556. This paper was recommended by Associate Editor R. Otten. The author is with the Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 5001 1 IJSA. Publisher Item Identifier S 0278-0070(96)057 19-3.