Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities

Sriram Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Saurabh Kumar, Ram Krishnamurthy, Harish Krishnamurthy, James Tschanz, Vivek De, Chris H. Kim

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

The system-on-chip (SoC) designs for future Internet of Things (IoT) systems, spanning client platforms to cloud datacenters, need to deliver uncompromising and scalable performance with extreme energy efficiency for diverse workloads and applications, while satisfying a wide range of energy budgets, as well as platform cooling and power delivery constraints. Low-latency, burst-mode responsiveness, and scalable high-throughput performance must be delivered on demand for a range of thread-parallel, task-parallel, and data-parallel workloads covering traditional and emerging applications. This article discusses the challenges and opportunities for many-core SoC design in scaled CMOS process operating over a wide voltage-frequency range including near-threshold-voltage (NTV) that can meet the compute demands of the future at scale, flexibly, and efficiently. This article covers: 1) circuit design techniques for NTV cores; 2) mitigation techniques for within-die parameter variations via multivoltage frequency schemes; 3) digital integrated voltage regulators (VRs) for fine-grain and wide-range voltage modulation; and 4) radiation-induced soft error rate (SER) characterization and mitigation techniques to enable reliable operation at NTV. Silicon prototype examples will be used to illustrate the different techniques and highlight future research directions.

Original languageEnglish (US)
Article number9374565
Pages (from-to)843-856
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume29
Issue number5
DOIs
StatePublished - May 1 2021

Bibliographical note

Publisher Copyright:
© 1993-2012 IEEE.

Keywords

  • Digital low dropout (LDO)
  • low-power
  • low-voltage SRAM memory circuits
  • minimum-energy design
  • near-threshold-voltage (NTV) computing
  • power-performance
  • resilient adaptive computing
  • soft error rate (SER) characterization
  • variation-aware many-core dynamic-voltage-frequency scaling (DVFS)

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