Where is the Achilles heel under circuit aging

Ketul Sutaria; Athul Ramkumar; Rongjun Zhu; Yu Cao

doi:10.1109/ISVLSI.2014.106

Where is the Achilles heel under circuit aging

Ketul Sutaria, Athul Ramkumar, Rongjun Zhu, Yu Cao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

The degradation of IC reliability is usually a gradual process, only causing moderate increase in the failure rate over time. However, under some specific circumstance, the degradation rate can be dramatically accelerated, leading to some catastrophic phenomena in digital and analog designs. Based on silicon data, this paper highlights such critical conditions, including severe frequency shift under DVS, asymmetric aging due to clock gating, and bias runaway. The analysis and solutions to these issues are vitally important to reliable IC design practice.

Original language	English (US)
Title of host publication	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Publisher	IEEE Computer Society
Pages	278-279
Number of pages	2
ISBN (Electronic)	9781479937639
DOIs	https://doi.org/10.1109/ISVLSI.2014.106
State	Published - Sep 18 2014
Externally published	Yes
Event	2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 - Tampa, United States Duration: Jul 9 2014 → Jul 11 2014

Conference

Conference	2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014
Country/Territory	United States
City	Tampa
Period	7/9/14 → 7/11/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

Keywords

BTI
DVS
HCI
asymmetric aging
bias runaway
circuit aging

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10.1109/ISVLSI.2014.106

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abstract = "The degradation of IC reliability is usually a gradual process, only causing moderate increase in the failure rate over time. However, under some specific circumstance, the degradation rate can be dramatically accelerated, leading to some catastrophic phenomena in digital and analog designs. Based on silicon data, this paper highlights such critical conditions, including severe frequency shift under DVS, asymmetric aging due to clock gating, and bias runaway. The analysis and solutions to these issues are vitally important to reliable IC design practice.",

keywords = "BTI, DVS, HCI, asymmetric aging, bias runaway, circuit aging",

author = "Ketul Sutaria and Athul Ramkumar and Rongjun Zhu and Yu Cao",

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year = "2014",

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doi = "10.1109/ISVLSI.2014.106",

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AU - Ramkumar, Athul

AU - Zhu, Rongjun

AU - Cao, Yu

PY - 2014/9/18

Y1 - 2014/9/18

N2 - The degradation of IC reliability is usually a gradual process, only causing moderate increase in the failure rate over time. However, under some specific circumstance, the degradation rate can be dramatically accelerated, leading to some catastrophic phenomena in digital and analog designs. Based on silicon data, this paper highlights such critical conditions, including severe frequency shift under DVS, asymmetric aging due to clock gating, and bias runaway. The analysis and solutions to these issues are vitally important to reliable IC design practice.

AB - The degradation of IC reliability is usually a gradual process, only causing moderate increase in the failure rate over time. However, under some specific circumstance, the degradation rate can be dramatically accelerated, leading to some catastrophic phenomena in digital and analog designs. Based on silicon data, this paper highlights such critical conditions, including severe frequency shift under DVS, asymmetric aging due to clock gating, and bias runaway. The analysis and solutions to these issues are vitally important to reliable IC design practice.

KW - BTI

KW - DVS

KW - HCI

KW - asymmetric aging

KW - bias runaway

KW - circuit aging

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DO - 10.1109/ISVLSI.2014.106

M3 - Conference contribution

AN - SCOPUS:84908218260

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EP - 279

BT - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

PB - IEEE Computer Society

T2 - 2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014

Y2 - 9 July 2014 through 11 July 2014

ER -

Where is the Achilles heel under circuit aging

Abstract

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Keywords

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