Wafer-scale high- k SrTiO3 dielectrics with rational barrier-layer design for low leakage and high charge density

High-k oxides such as SrTiO₃ promise large capacitance, but their dielectric response is often limited by leakage currents due to reduced bandgaps. We show that introducing a thin barrier layer beneath SrTiO₃ is a simple and effective way to suppress leakage and increase charge density. Using hybrid molecular beam epitaxy, we grew uniform SrTiO₃ films on Nb:SrTiO₃, CaSnO₃/Nb:SrTiO₃, and 2-in. SiO₂/p-Si stacks to directly compare how different barrier layers influence device behavior. Both CaSnO₃ and SiO₂ reduce leakage, but the ultra-wide-bandgap SiO₂ layer enables much higher operating voltages, yielding charge densities exceeding 5 × 10¹³ cm⁻² at room temperature—more than a fivefold enhancement compared to devices without a barrier layer. This improvement comes with a predictable trade-off: the lower dielectric constant of SiO₂ reduces overall capacitance, making its thickness an important design parameter. Together, these results demonstrate that rational barrier-layer engineering—including wafer-scale integration on Si—provides a clear pathway to achieving higher charge densities in SrTiO₃-based dielectric devices.