Wafer level interconnects for 3D Packaging

Swagata Riki Banerjee; Rhonda Franklin Drayton

Wafer level interconnects for 3D Packaging

Swagata Riki Banerjee, Rhonda Franklin Drayton

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

2 Scopus citations

Abstract

A hybrid electrical package is compared to monolithic designs to isolate the effects of wirebond parasitics and modularity. The monolithic designs produce 3.2 dB of insertion loss at 50 GHz, which indicates minimal loss due to wirebonds. The hybrid design insertion loss is within 0.5 dB of the reference case up to 40 GHz. The response is oscillatory above this frequency due to complex substrate transitions. Quasi-static modeling techniques are also used to model the wirebond effects with standard CAD tools.

Original language	English (US)
Pages (from-to)	1513-1518
Number of pages	6
Journal	Proceedings - Electronic Components and Technology Conference
Volume	2
State	Published - Dec 27 2004
Event	2004 Proceedings - 54th Electronic Components and Technology Conference - Las Vegas, NV, United States Duration: Jun 1 2004 → Jun 4 2004

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title = "Wafer level interconnects for 3D Packaging",

abstract = "A hybrid electrical package is compared to monolithic designs to isolate the effects of wirebond parasitics and modularity. The monolithic designs produce 3.2 dB of insertion loss at 50 GHz, which indicates minimal loss due to wirebonds. The hybrid design insertion loss is within 0.5 dB of the reference case up to 40 GHz. The response is oscillatory above this frequency due to complex substrate transitions. Quasi-static modeling techniques are also used to model the wirebond effects with standard CAD tools.",

author = "Banerjee, {Swagata Riki} and Drayton, {Rhonda Franklin}",

year = "2004",

month = dec,

day = "27",

language = "English (US)",

volume = "2",

pages = "1513--1518",

journal = "Proceedings - Electronic Components and Technology Conference",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2004 Proceedings - 54th Electronic Components and Technology Conference ; Conference date: 01-06-2004 Through 04-06-2004",

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T1 - Wafer level interconnects for 3D Packaging

AU - Banerjee, Swagata Riki

AU - Drayton, Rhonda Franklin

PY - 2004/12/27

Y1 - 2004/12/27

N2 - A hybrid electrical package is compared to monolithic designs to isolate the effects of wirebond parasitics and modularity. The monolithic designs produce 3.2 dB of insertion loss at 50 GHz, which indicates minimal loss due to wirebonds. The hybrid design insertion loss is within 0.5 dB of the reference case up to 40 GHz. The response is oscillatory above this frequency due to complex substrate transitions. Quasi-static modeling techniques are also used to model the wirebond effects with standard CAD tools.

AB - A hybrid electrical package is compared to monolithic designs to isolate the effects of wirebond parasitics and modularity. The monolithic designs produce 3.2 dB of insertion loss at 50 GHz, which indicates minimal loss due to wirebonds. The hybrid design insertion loss is within 0.5 dB of the reference case up to 40 GHz. The response is oscillatory above this frequency due to complex substrate transitions. Quasi-static modeling techniques are also used to model the wirebond effects with standard CAD tools.

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M3 - Conference article

AN - SCOPUS:10444221763

VL - 2

SP - 1513

EP - 1518

JO - Proceedings - Electronic Components and Technology Conference

JF - Proceedings - Electronic Components and Technology Conference

SN - 0569-5503

T2 - 2004 Proceedings - 54th Electronic Components and Technology Conference

Y2 - 1 June 2004 through 4 June 2004

ER -

Wafer level interconnects for 3D Packaging

Abstract

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