VLSI implementation-oriented (3,k)-regular low-density parity-check codes

T. Zhang, K. K. Parhi

Research output: Contribution to conferencePaperpeer-review

60 Scopus citations

Abstract

In the past few years, Gallager's Low-Density Parity-Check (LDPC) codes received a lot of attention and many efforts have been devoted to analyze and improve their error-correcting performance. However, little consideration has been given to the LDPC decoder VLSI implementation. The straightforward fully parallel decoder architecture usually incurs too high complexity for many practical purposes and should be transformed to a partly parallel realization. Unfortunately, due to the randomness of LDPC codes, it's nearly impossible to develop an effective transformation for an arbitrary given LDPC code. In this paper, we propose a joint code and decoder design approach to construct a class of (3,k)-regular LDPC codes which exactly fit to a partly parallel decoder implementation and have a very good performance. Moreover, for such LDPC codes, we propose a systematic efficient encoding scheme by effectively exploiting the sparseness of its parity check matrix.

Original languageEnglish (US)
Pages25-36
Number of pages12
StatePublished - 2001
EventIEEE Workshop on Signal Processing Systems- Design and Implementation-(SIPS) 2001 - Antwerp, Belgium
Duration: Oct 26 2001Oct 28 2001

Other

OtherIEEE Workshop on Signal Processing Systems- Design and Implementation-(SIPS) 2001
CountryBelgium
CityAntwerp
Period10/26/0110/28/01

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