VLSI implementation of a 100 MHz pipelined ADPCM codec chip

N. R. Shanbhag; K. K. Parhi

doi:10.1109/VLSISP.1993.404496

VLSI implementation of a 100 MHz pipelined ADPCM codec chip

N. R. Shanbhag
, K. K. Parhi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

The VLSI implementation of a pipelined adaptive differential pulse-code modulation (ADPCM) video codec is described. The architecture for the ADPCM codec had been developed previously via the relaxed look-ahead technique. The results of this technique is a bit-parallel and bit-level pipelined architecture with minimal hardware overhead. All the arithmetic units employ redundant authors for low-latency, carry-free computatron. The pipelining latches are true single-phase and edge-triggered with a very compact structure. The pipelined ADPCM chip is designed in 1.2μ CMOS technology, with a total area of 5.6 × 8.8 mm², an active area of 5.1 × 8.2 mm² (136,000 transistors) and a projected speed of 100 MHz. This chip can be configured both as an encoder and a decoder. The codec has a compression ratio of a 8:3 for a 256 × 256 image frame.

Original language	English (US)
Title of host publication	Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	114-122
Number of pages	9
ISBN (Electronic)	0780309960, 9780780309968
DOIs	https://doi.org/10.1109/VLSISP.1993.404496
State	Published - 1993
Event	6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993 - Veldhoven, Netherlands Duration: Oct 20 1993 → Oct 22 1993

Publication series

Name	Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993

Conference

Conference	6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993
Country/Territory	Netherlands
City	Veldhoven
Period	10/20/93 → 10/22/93

Bibliographical note

Funding Information:
This research was supported by the Army Research Office by contract number DAAL03-90-G-0063 and the National Science Foundation under contract number MIP-9258670.

Publisher Copyright:
© 1993 IEEE.

Publisher link

10.1109/VLSISP.1993.404496

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Shanbhag, N. R., & Parhi, K. K. (1993). VLSI implementation of a 100 MHz pipelined ADPCM codec chip. In Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993 (pp. 114-122). Article 404496 (Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSISP.1993.404496

VLSI implementation of a 100 MHz pipelined ADPCM codec chip. / Shanbhag, N. R.; Parhi, K. K.
Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993. Institute of Electrical and Electronics Engineers Inc., 1993. p. 114-122 404496 (Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shanbhag, NR & Parhi, KK 1993, VLSI implementation of a 100 MHz pipelined ADPCM codec chip. in Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993., 404496, Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993, Institute of Electrical and Electronics Engineers Inc., pp. 114-122, 6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993, Veldhoven, Netherlands, 10/20/93. https://doi.org/10.1109/VLSISP.1993.404496

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abstract = "The VLSI implementation of a pipelined adaptive differential pulse-code modulation (ADPCM) video codec is described. The architecture for the ADPCM codec had been developed previously via the relaxed look-ahead technique. The results of this technique is a bit-parallel and bit-level pipelined architecture with minimal hardware overhead. All the arithmetic units employ redundant authors for low-latency, carry-free computatron. The pipelining latches are true single-phase and edge-triggered with a very compact structure. The pipelined ADPCM chip is designed in 1.2μ CMOS technology, with a total area of 5.6 × 8.8 mm2, an active area of 5.1 × 8.2 mm2 (136,000 transistors) and a projected speed of 100 MHz. This chip can be configured both as an encoder and a decoder. The codec has a compression ratio of a 8:3 for a 256 × 256 image frame.",

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N2 - The VLSI implementation of a pipelined adaptive differential pulse-code modulation (ADPCM) video codec is described. The architecture for the ADPCM codec had been developed previously via the relaxed look-ahead technique. The results of this technique is a bit-parallel and bit-level pipelined architecture with minimal hardware overhead. All the arithmetic units employ redundant authors for low-latency, carry-free computatron. The pipelining latches are true single-phase and edge-triggered with a very compact structure. The pipelined ADPCM chip is designed in 1.2μ CMOS technology, with a total area of 5.6 × 8.8 mm2, an active area of 5.1 × 8.2 mm2 (136,000 transistors) and a projected speed of 100 MHz. This chip can be configured both as an encoder and a decoder. The codec has a compression ratio of a 8:3 for a 256 × 256 image frame.

AB - The VLSI implementation of a pipelined adaptive differential pulse-code modulation (ADPCM) video codec is described. The architecture for the ADPCM codec had been developed previously via the relaxed look-ahead technique. The results of this technique is a bit-parallel and bit-level pipelined architecture with minimal hardware overhead. All the arithmetic units employ redundant authors for low-latency, carry-free computatron. The pipelining latches are true single-phase and edge-triggered with a very compact structure. The pipelined ADPCM chip is designed in 1.2μ CMOS technology, with a total area of 5.6 × 8.8 mm2, an active area of 5.1 × 8.2 mm2 (136,000 transistors) and a projected speed of 100 MHz. This chip can be configured both as an encoder and a decoder. The codec has a compression ratio of a 8:3 for a 256 × 256 image frame.

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VLSI implementation of a 100 MHz pipelined ADPCM codec chip

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