VLSI implementation of a 100 MHz pipelined ADPCM codec chip

N. R. Shanbhag, K. K. Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

The VLSI implementation of a pipelined adaptive differential pulse-code modulation (ADPCM) video codec is described. The architecture for the ADPCM codec had been developed previously via the relaxed look-ahead technique. The results of this technique is a bit-parallel and bit-level pipelined architecture with minimal hardware overhead. All the arithmetic units employ redundant authors for low-latency, carry-free computatron. The pipelining latches are true single-phase and edge-triggered with a very compact structure. The pipelined ADPCM chip is designed in 1.2μ CMOS technology, with a total area of 5.6 × 8.8 mm2, an active area of 5.1 × 8.2 mm2 (136,000 transistors) and a projected speed of 100 MHz. This chip can be configured both as an encoder and a decoder. The codec has a compression ratio of a 8:3 for a 256 × 256 image frame.

Original languageEnglish (US)
Title of host publicationProceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages114-122
Number of pages9
ISBN (Electronic)0780309960, 9780780309968
DOIs
StatePublished - Jan 1 1993
Event6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993 - Veldhoven, Netherlands
Duration: Oct 20 1993Oct 22 1993

Publication series

NameProceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993

Conference

Conference6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993
CountryNetherlands
CityVeldhoven
Period10/20/9310/22/93

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