VLSI architectures for the restricted boltzmann machine

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Abstract

Neural network (NN) systems are widely used in many important applications ranging from computer vision to speech recognition. To date, most NN systems are processed by general processing units like CPUs or GPUs. However, as the sizes of dataset and network rapidly increase, the original software implementations suffer from long training time. To overcome this problem, specialized hardware accelerators are needed to design high-speed NN systems. This article presents an efficient hardware architecture of restricted Boltzmann machine (RBM) that is an important category of NN systems. Various optimization approaches at the hardware level are performed to improve the training speed. As-soon-as-possible and overlappedscheduling approaches are used to reduce the latency. It is shown that, compared with the flat design, the proposedRBMarchitecture can achieve 50% reduction in training time. In addition, an on-the-fly computation scheme is also used to reduce the storage requirement of binary and stochastic states by several hundreds of times. Then, based on the proposed approach, a 784-2252 RBM design example is developed for MNIST handwritten digit recognition dataset. Analysis shows that the VLSI design of RBM achieves significant improvement in training speed and energy efficiency as compared to CPU/GPU-based solution.

Original languageEnglish (US)
Article number35
JournalACM Journal on Emerging Technologies in Computing Systems
Volume13
Issue number3
DOIs
StatePublished - May 2017

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Keywords

  • Restricted Boltzmann machine (RBM)
  • VLSI
  • high-speed
  • memory reduction
  • neural network (NN)
  • overlapped-scheduling
  • reduced-latency

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