This paper presents two classes of novel VLSI architectures, referred to as the folded architecture and the digit-serial architecture, for implementation of one-and two-dimensional discrete wavelet transforms. In the one-dimensional folded architecture, the computations of all wavelet levels are folded to the same low-pass and high-pass filters. The number of registers in the folded architecture is minimized by the use of a generalized life time analysis. The converter units are synthesized with minimum number of registers using forward-backward allocation. The advantage of the folded architecture is low latency and its drawbacks are increased hardware area, less than 100% hardware utilization, and complex routing and interconnection required by the converters used in this architecture. These drawbacks are eliminated in the alternate digit-serial architecture which requires simpler control circuits, routing, and interconnection, achieves complete hardware utilization, and requires lower power, at the expense of an increase in the system latency and some constraints on the wordlength. In latency-critical applications, we propose the use of the folded architecture. If latency is not so critical, we propose the use of the digit-serial architecture. The use of a combined folded and digit-serial architecture is proposed for implementation of two-dimensional discrete wavelet transforms.
|Original language||English (US)|
|Number of pages||12|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Jun 1993|