In this paper, an area efficient high speed Viterbi decoder architecture, which is based on the state-parallel architecture with register exchange path memory structure, for interleaved convolutional code is proposed. By replacing each delay (or storage) element in state metrics memory (or path metrics memory) and path memory (or survival memory) with I delays, interleaved Viterbi decoder is obtained. The decoding speed of this decoder architecture is as fast as the operating clock speed. The latency of proposed interleaved Viterbi decoder is "decoding depth (DD) × interleaving degree (I)", which is linearly increased with the interleaving degree 1.
|Original language||English (US)|
|Number of pages||4|
|Journal||Conference Record of the Asilomar Conference on Signals, Systems and Computers|
|State||Published - Dec 1 2002|
|Event||The Thirty-Sixth Asilomar Conference on Signals Systems and Computers - Pacific Groove, CA, United States|
Duration: Nov 3 2002 → Nov 6 2002