The processing and performance of Schottky diodes formed from arrays of vertical Ge nanowires (NWs) grown on Ge and Si substrates are reported. The goal of this work is to investigate CMOS compatible processes for integrating NWs as components of vertically scaled integrated circuits, and elucidate transport in vertical Schottky NWs. Vertical phosphorus (P) doped Ge NWs were grown using vapor-liquid-solid epitaxy, and nickel (Ni)-Ge Schottky contacts were made to the tops of the NWs. Current-voltage (I-V) characteristics were measured for variable ranges of NW diameters and numbers of nanowires in the arrays, and the I-V characteristics were fit using modified thermionic emission theory to extract the barrier height and ideality factor. As grown NWs did not show rectifying behavior due to the presence of heavy P side-wall doping during growth, resulting in a tunnel contact. After sidewall etching using a dilute peroxide solution, rectifying behavior was obtained. Schottky barrier heights of 0.3-0.4 V and ideality factors close to 2 were extracted using thermionic emission theory, although the model does not give an accurate fit across the whole bias range. Attempts to account for enhanced side-wall conduction due to non-uniform P doping profile during growth through a simple shunt resistance improve the fit, but are still insufficient to provide a good fit. Full three-dimensional numerical modeling using Silvaco Atlas indicates that at least part of this effect is due to the presence of fixed charge and acceptor like traps on the NW surface, which leads to effectively high ideality factors.