Verifying equivalence of digital signal processing circuits

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

Verifying the equivalence of digital signal processing circuits is not only important in designing architectures, but also in designing secure circuits. If the functionality equivalence cannot be easily verified, then the security can be improved. In this paper, we present novel use of high-level transformations to hide the functionalities of DSP circuits, which include retiming, pipelining, folding, unfolding, and interleaving. We show that we can design circuits which are harder to reverse engineer by adopting high-level transformations. However, other techniques, such as modifying the switch instances, adding dummy loops, and manipulating inputs, can also be exploited for both verifying equivalence as well as designing secure circuits.

Original languageEnglish (US)
Title of host publicationConference Record of the 46th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2012
Pages99-103
Number of pages5
DOIs
StatePublished - Dec 1 2012
Event46th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2012 - Pacific Grove, CA, United States
Duration: Nov 4 2012Nov 7 2012

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
ISSN (Print)1058-6393

Other

Other46th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2012
CountryUnited States
CityPacific Grove, CA
Period11/4/1211/7/12

Keywords

  • Functionality Equivalence
  • Hierarchical Folding
  • High-Level Transformation
  • Reverse Engineering
  • Security

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  • Cite this

    Parhi, K. K. (2012). Verifying equivalence of digital signal processing circuits. In Conference Record of the 46th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2012 (pp. 99-103). [6488967] (Conference Record - Asilomar Conference on Signals, Systems and Computers). https://doi.org/10.1109/ACSSC.2012.6488967