Abstract
As technology scales, negative bias temperature instability (NBTI) has become a major reliability concern for circuit designers. And the growing process variations can no longer be ignored. Meanwhile, reducing power consumption remains to be one of the design goals. In this paper, a variation-aware supply voltage assignment (SVA) technique combining dual V dd assignment and dynamic V dd scaling is proposed on a statistical platform, to minimize circuit power under an aging-aware timing constraint. The experimental results show that our SVA technique can mitigate on average 62% of the NBTI-induced circuit delay degradation. Compared with guard-banding and single V dd scaling approaches, our approach saves more energy.
| Original language | English (US) |
|---|---|
| Article number | 6042352 |
| Pages (from-to) | 2143-2147 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 20 |
| Issue number | 11 |
| DOIs | |
| State | Published - 2012 |
| Externally published | Yes |
Bibliographical note
Funding Information:Manuscript received November 16, 2010; revised March 11, 2011; accepted September 03, 2011. Date of publication October 13, 2011; date of current version July 27, 2012. This work was supported by National Key Technological Program of China (2008ZX01035-001, 2010ZX01030-001) and National Natural Science Foundation of China (60870001). The work of Y. Ma was supported by National Natural Science Foundation of China (61076035).
Keywords
- Dynamic power
- leakage power
- negative bias temperature instability (NBTI)
- supply voltage assignment (SVA)