Variation-aware routing for FPGAs

Satish Sivaswamy, Kia Bazargan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the effects of variations. The FPGA community on the other hand, has only recently started focussing on the effects of variations. This paper presents a comparative study of the impact of variations on designs mapped to FPGAs and ASICs to get a measure of the severity of the problem in both the FPGA and ASIC domains. We also propose a variation aware router that reduces the yield loss by 7.61X, or the circuit delay by 3.95% for the same yield for the MCNC benchmarks.

Original languageEnglish (US)
Title of host publicationFPGA 2007
Subtitle of host publicationFifteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Pages71-79
Number of pages9
DOIs
StatePublished - Oct 2 2007
EventFPGA 2007: Fifteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - Monterey, CA, United States
Duration: Feb 18 2007Feb 20 2007

Publication series

NameACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Conference

ConferenceFPGA 2007: Fifteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
CountryUnited States
CityMonterey, CA
Period2/18/072/20/07

Keywords

  • FPGA routing
  • Statistical timing analysis

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    Sivaswamy, S., & Bazargan, K. (2007). Variation-aware routing for FPGAs. In FPGA 2007: Fifteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (pp. 71-79). [1216930] (ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA). https://doi.org/10.1145/1216919.1216930