Variation aware performance analysis of gain cell embedded DRAMs

Wei Zhang, Ki Chul Chun, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

Gain cell embedded DRAMs are twice as dense as 6T SRAMs, are logic compatible, have decoupled read and write paths providing good low voltage margin, and can drive long bitlines with gain. In this work, we present a variation study of gain cell eDRAM performance using an industrial 1.2V, 65nm low power CMOS process. Two methods are proposed to analyze eDRAM performance which can be used for designing variation tolerant eDRAM circuits, developing redundancy techniques, and guiding the device optimization procedure.

Original languageEnglish (US)
Title of host publicationISLPED'10 - Proceedings of the 16th ACM/IEEE International Symposium on Low-Power Electronics and Design
Pages19-24
Number of pages6
DOIs
StatePublished - Oct 21 2010
Event16th ACM/IEEE International Symposium on Low-Power Electronics and Design, ISLPED'10 - Austin, TX, United States
Duration: Aug 18 2010Aug 20 2010

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

Other16th ACM/IEEE International Symposium on Low-Power Electronics and Design, ISLPED'10
CountryUnited States
CityAustin, TX
Period8/18/108/20/10

Keywords

  • Bitline delay
  • Embedded DRAM
  • Gain cell
  • Monte Carlo simulation
  • Process variation

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