Using stochastic computing to reduce the hardware requirements for a restricted boltzmann machine classifier

Artificial neural networks are powerful computational sys- tems with interconnected neurons. Generally, these net- works have a very large number of computation nodes which forces the designer to use software-based implementations. However, the software based implementations are offline and not suitable for portable or real-time applications. Experi- ments show that compared with the software based imple- mentations, FPGA-based systems can greatly speed up the computation time, making them suitable for real-time situa- tions and portable applications. However, the FPGA imple- mentation of neural networks with a large number of nodes is still a challenging task. In this paper, we exploit stochastic bit streams in the Re- stricted Boltzmann Machine (RBM) to implement the clas- sification of the RBM handwritten digit recognition applica- tion completely on an FPGA. We use finite state machine- based (FSM) stochastic circuits to implement the required sigmoid function and use the novel stochastic computing approach to perform all large matrix multiplications. Ex- perimental results show that the proposed stochastic archi- tecture has much more potential for tolerating faults while requiring much less hardware compared to the currently un-implementable deterministic binary approach when the RBM consists of a large number of neurons. Exploiting the features of stochastic circuits, our implementation achieves much better performance than a software-based approach.