Using randomization to cope with circuit uncertainty

Hamid Safizadeh, Mohammad Tahghighi, Ehsan K. Ardestani, Gholamhossein Tavasoli, Kia Bazargan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Future computing systems will feature many cores that run fast, but might show more faults compared to existing CMOS technologies. New software methodologies must be adopted to utilize communication bandwidth and the computational power of few slow, reliable cores that could be employed in such systems to verify the results of the fast, faulty cores. Employing the traditional Triple Module Redundancy (TMR) at core instruction level would not be as effective due to its blind replication of computations. We propose two software development methods that utilize what we call Smart TMR (STMR) and fingerprinting to statistically monitor the results of computations and selectively replicate computations that exhibit faults. Experimental results show significant speedup and reliability improvement over traditional TMR approaches.

Original languageEnglish (US)
Title of host publicationProceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages815-820
Number of pages6
ISBN (Print)9783981080155
DOIs
StatePublished - 2009
Event2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 - Nice, France
Duration: Apr 20 2009Apr 24 2009

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
CountryFrance
CityNice
Period4/20/094/24/09

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    Safizadeh, H., Tahghighi, M., Ardestani, E. K., Tavasoli, G., & Bazargan, K. (2009). Using randomization to cope with circuit uncertainty. In Proceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 (pp. 815-820). [5090775] (Proceedings -Design, Automation and Test in Europe, DATE). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/date.2009.5090775