Unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area

Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

This paper examines the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification under the standard-cell paradigm. This is effected by appropriately selecting a size for each gate in the circuit from a standard-cell library, and by adjusting the delays between the central clock distribution node and individual flip-flops. Traditional methods treat these two problems separately, which may lead to very sub-optimal solutions in some cases. Experimental results show that by considering the two problems together, it is not only possible to reduce the optimized circuit area, but also to achieve faster clocking frequencies. We also address the problem of making this work applicable to very large synchronous sequential circuits by partitioning these circuits to reduce the computational complexity.

Original languageEnglish (US)
Title of host publicationProc 1993 IEEE ACM Int Conf Comput Aided Des
Editors Anon
PublisherPubl by IEEE
Pages220-223
Number of pages4
ISBN (Print)0818644923
StatePublished - Dec 1 1993
EventProceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design - Santa Clara, CA, USA
Duration: Nov 7 1993Nov 11 1993

Publication series

NameProc 1993 IEEE ACM Int Conf Comput Aided Des

Other

OtherProceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design
CitySanta Clara, CA, USA
Period11/7/9311/11/93

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