Unfolding and retiming for high-level DSP synthesis

Lori E. Lucke, Andrew P. Brown, Keshab K. Parhi

Research output: Contribution to journalConference article

11 Citations (Scopus)

Abstract

A method of determining the minimum unfolding factor needed to synthesize a data path for a given sample rate is presented. Minimizing the unfolding factor is important because the time complexity for scheduling and allocation increases linearly with the unfolding factor. The authors discuss the iterative algorithm which calculates the minimum unfolding factor necessary to achieve a given sample rate with and without retiming. This algorithm is utilized within the MARS (the Minnesota architecture synthesis) design system to preprocess a dataflow graph prior to resource scheduling and allocation.

Original languageEnglish (US)
Pages (from-to)2351-2354
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
StatePublished - Dec 1 1991
Event1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore
Duration: Jun 11 1991Jun 14 1991

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Unfolding and retiming for high-level DSP synthesis. / Lucke, Lori E.; Brown, Andrew P.; Parhi, Keshab K.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 4, 01.12.1991, p. 2351-2354.

Research output: Contribution to journalConference article

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