Understanding the impact of transistor-level BTI variability

Jianxin Fang, Sachin S Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

Recent work has shown large variations due to bias-temperature instability (BTI) at the device level, and we study its impact on the behavior of larger circuits. We propose an analytical method that is over 600x faster than Monte Carlo simulation and accurate for technologies down to 16nm, and demonstrate it on circuits with up to 68,000 transistors. Results show that the impact of BTI variability at the circuit level is significantly smaller than at the device level, but increases with device downscaling.

Original languageEnglish (US)
Title of host publication2012 IEEE International Reliability Physics Symposium, IRPS 2012
DOIs
StatePublished - Sep 28 2012
Event2012 IEEE International Reliability Physics Symposium, IRPS 2012 - Anaheim, CA, United States
Duration: Apr 15 2012Apr 19 2012

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Other

Other2012 IEEE International Reliability Physics Symposium, IRPS 2012
CountryUnited States
CityAnaheim, CA
Period4/15/124/19/12

Keywords

  • Bias-Temperature Instability (BTI)
  • Degradation Analysis
  • Digital Circuit Delay
  • Variability

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