We present an ultra-low-power, delayed least mean square (DLMS) adaptive filter operating in the subthreshold region for hearing aid applications. Subthreshold operation was accomplished by using a parallel architecture with pseudo nMOS logic style. The parallel architecture enabled us to operate the system at a lower clock rate and reduced supply voltage while maintaining the same throughput. Pseudo nMOS logic operating in the subthreshold region (subpseudo nMOS) provided better power-delay product than subthreshold CMOS (sub-CMOS) logic. Simulation results show that the DLMS adaptive filter can operate at 22 kHz using a 400-mV supply voltage to achieve 91% improvement in power compared to a nonparallel, CMOS implementation. To validate the robust operation of subthreshold logics, a 0.35 μm, 23.1 kHz, 21.4 nW, 8 × 8 carry save array multiplier test chip was fabricated where an adaptive body biasing scheme is used for compensating process, supply and temperature variations. The test chip showed stable operation at a supply voltage of 0.30 V, which is even lower than the threshold voltages of the pMOS (0.82 V) and nMOS (0.67 V) transistors.
|Original language||English (US)|
|Number of pages||10|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Dec 2003|
Bibliographical noteFunding Information:
Manuscript received January 23, 2002; revised October 16, 2002. This work was supported in part by the Semiconductor Research Corporation under Contract 98-HJ-638 and in part by the National Science Foundation under Contract CCR-9901152.
- Adaptive filter
- Parallel architecture
- Subpseudo nMOS
- Subthreshold CMOS (sub-CMOS)
- Subthreshold operation