Ultra-low leakage silicon-on-insulator technology for 65 nm node and beyond

Jin Cai, Amlan Majumdar, David Dobuzinsky, Tak H. Ning, Steven J. Koester, Wilfried E. Haensch

Research output: Contribution to journalConference articlepeer-review

6 Scopus citations


We report 65 nm ground-rule, partially depleted, low-power silicon-on-insulator (LPSOI) CMOS devices with total leakage current I OFF down to 10 pA/μm at supply voltage VDD = 1.2 V. NFET/PFET drive current IDSAT = 550/250 μA/tm at IOFF = 100 pA/μm and gate length LG ∼ 55 nm are achieved with a single tensile liner film. Innovative junction engineering techniques such as low-damage junction pre-amorphization implants (PAI), source-side high-damage PAI, high-energy halo, and drain-side tilted source/drain (S/D) implants are evaluated for their effectiveness in minimizing SOI floating body effect for low leakage design. Our result suggests that there is no fundamental limit for low leakage application of SOI.

Original languageEnglish (US)
Article number4419097
Pages (from-to)907-910
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
StatePublished - Dec 1 2007
Event2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States
Duration: Dec 10 2007Dec 12 2007


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