Abstract
Scaling in the deep submicron (DSM) regime has fundamentally altered the primary issues affecting VLSI design. Logical-physical codesign is essential with great dependence between logic-level optimizations and the actual physical design. The problems encountered in the DSM design and the computer aided design (CAD) strategies used to overcome them were discussed.
Original language | English (US) |
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Title of host publication | Proceedings of the IEEE International Conference on VLSI Design |
Pages | 3-4 |
Number of pages | 2 |
State | Published - Jan 1 2001 |
Event | 14th International Conference on VLSI Design (VLSI DESIGN 2001) - Bangalore, India Duration: Jan 3 2001 → Jan 7 2001 |
Other
Other | 14th International Conference on VLSI Design (VLSI DESIGN 2001) |
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Country/Territory | India |
City | Bangalore |
Period | 1/3/01 → 1/7/01 |