Tutorial: High-speed interconnect technology: On-chip and off-chip

Sachin S Sapatnekar, Jaijeet Roychowdhury, Ramesh Harjani

Research output: Contribution to journalArticlepeer-review

Abstract

Computing needs for business, communications and gaming applications continue to increase. Innovative IC processing and fabrication techniques developed by researchers from around the globe have allowed microprocessor manufacturers to continue their technology scaling trends such that current processors have hundreds of millions of transistors and have clock rates in multiple giga-Hertz. However, interconnect delays, both on-chip and off-chip, are quickly becoming the bottleneck and will limit the maximum performance attainable from device scaling. On-chip RC and RLC delays are becoming significantly larger than gate delays forcing circuit designers to alter basic design methodologies and system designers to alter traditional architectures and design paradigms. This tutorial provides both timely and relevant information for both on-chip and off-chip interconnect technologies. Topics covered in this tutorial include on-chip wire modeling, delay calculations, optimization and design techniques; off-chip interconnect and cross-talk modeling, high-speed I/O transceivers and drivers, binary and multi-level signaling, clock and data recovery circuits, jitter and phase noise modeling. The speakers bring both academic and industrial experience to bear on this critical topic. The tutorial is aimed at senior students and practicing engineers interested in high-performance circuit designs.

Original languageEnglish (US)
Number of pages1
JournalProceedings of the IEEE International Conference on VLSI Design
StatePublished - Dec 1 2005

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