TurboTiling: Leveraging prefetching to boost performance of tiled codes

Keyphrases

• Prefetching 100%
• Last-level Cache 100%
• Caching 50%
• Hardware Prefetcher 50%
• Tile Size 50%
• Tile Algorithms 50%
• Multicore Processors 25%
• Intel 25%
• Problem Size 25%
• Problem Domain 25%
• Temporal Locality 25%
• L1-L2 25%
• Size Selectivity 25%
• Streaming Data 25%
• L2 Cache 25%
• Access Pattern 25%
• Hardware Prefetching 25%
• Data Reuse 25%
• Loop Tiling 25%
• Conflict Misses 25%
• Data Access Pattern 25%
• Loop Blocking 25%
• Large Problem Size 25%
• Number of Cores 25%

Computer Science

• prefetching 100%
• Hardware Prefetcher 50%
• Multicore Processor 25%
• Data Streaming 25%
• L2 Cache 25%
• Access Pattern 25%
• Temporal Locality 25%
• Data Reuse 25%
• Loop Tiling 25%
• Conflict Miss 25%
• Data Access Pattern 25%
• Large Problem Size 25%
• Problem Domain 25%
• Combined Effect 25%
• Computer Hardware 25%