Transistor and pin reordering for gate oxide leakage reduction in dual T ox circuits

Anup Kumar Sultania; Dennis Sylvester; Sachin S Sapatnekar

doi:10.1109/ICCD.2004.1347927

Transistor and pin reordering for gate oxide leakage reduction in dual T _ox circuits

Anup Kumar Sultania, Dennis Sylvester, Sachin S Sapatnekar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Scopus citations

Abstract

Gate oxide tunneling current (I _gate) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce I _gate is to leverage dual T _ox processes where non-critical transistors are assigned a thicker T _ox. In this paper, we generate a leakage/delay tradeoff curve for dual T _ox circuits, and propose a transistor and pin reordering technique that has a minimal layout impact to further reduce the total leakage current up to 18% and I _gate. up to 26% without incurring any delay penalty.

Original language	English (US)
Title of host publication	Proceedings - IEEE International Conference on Computer Design
Subtitle of host publication	VLSI in Computers and Processors, ICCD 2004
Pages	228-233
Number of pages	6
DOIs	https://doi.org/10.1109/ICCD.2004.1347927
State	Published - 2004
Event	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004 - San Jose, CA, United States Duration: Oct 11 2004 → Oct 13 2004

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)	1063-6404

Other

Other	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004
Country/Territory	United States
City	San Jose, CA
Period	10/11/04 → 10/13/04

Publisher link

10.1109/ICCD.2004.1347927

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Cite this

Sultania, A. K., Sylvester, D., & Sapatnekar, S. S. (2004). Transistor and pin reordering for gate oxide leakage reduction in dual T _ox circuits. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004 (pp. 228-233). (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). https://doi.org/10.1109/ICCD.2004.1347927

Transistor and pin reordering for gate oxide leakage reduction in dual T _ox circuits. / Sultania, Anup Kumar; Sylvester, Dennis; Sapatnekar, Sachin S.
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004. 2004. p. 228-233 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sultania, AK, Sylvester, D & Sapatnekar, SS 2004, Transistor and pin reordering for gate oxide leakage reduction in dual T _ox circuits. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 228-233, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004, San Jose, CA, United States, 10/11/04. https://doi.org/10.1109/ICCD.2004.1347927

Sultania AK, Sylvester D, Sapatnekar SS. Transistor and pin reordering for gate oxide leakage reduction in dual T _ox circuits. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004. 2004. p. 228-233. (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). doi: 10.1109/ICCD.2004.1347927

Sultania, Anup Kumar ; Sylvester, Dennis ; Sapatnekar, Sachin S. / Transistor and pin reordering for gate oxide leakage reduction in dual T _ox circuits. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004. 2004. pp. 228-233 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

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