Tradeoffs between gate oxide leakage and delay for dual T _ox circuits

Gate oxide tunneling current (I _gate) will become the dominant component of leakage in CMOS circuits as the physical oxide thickness (T _ox) goes below 15Å. Increasing the value of T _ox reduces the leakage at the expense of an increase in delay, and a practical tradeoff between delay and leakage can be achieved by assigning one of the two permissible T _ox values to each transistor. In this paper, we propose an algorithm for dual T _ox assignment to optimize the total leakage power under delay constraints, and generate a leakage/delay tradeoff curve. As compared to the case where all transistors are set to low T _ox, our approach achieves an average leakage reduction of 83% under 100nm models.