Gate oxide tunneling current (I gate) will become the dominant component of leakage in CMOS circuits as the physical oxide thickness (T ox) goes below 15Å. Increasing the value of T ox reduces the leakage at the expense of an increase in delay, and a practical tradeoff between delay and leakage can be achieved by assigning one of the two permissible T ox values to each transistor. In this paper, we propose an algorithm for dual T ox assignment to optimize the total leakage power under delay constraints, and generate a leakage/delay tradeoff curve. As compared to the case where all transistors are set to low T ox, our approach achieves an average leakage reduction of 83% under 100nm models.
|Number of pages
|Proceedings - Design Automation Conference
|Published - 2004
|Proceedings of the 41st Design Automation Conference - San Diego, CA, United States
Duration: Jun 7 2004 → Jun 11 2004
- Dual T Circuits
- Leakage power