Tradeoffs between gate oxide leakage and delay for dual T ox circuits

Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar

Research output: Contribution to journalConference articlepeer-review

37 Scopus citations


Gate oxide tunneling current (I gate) will become the dominant component of leakage in CMOS circuits as the physical oxide thickness (T ox) goes below 15Å. Increasing the value of T ox reduces the leakage at the expense of an increase in delay, and a practical tradeoff between delay and leakage can be achieved by assigning one of the two permissible T ox values to each transistor. In this paper, we propose an algorithm for dual T ox assignment to optimize the total leakage power under delay constraints, and generate a leakage/delay tradeoff curve. As compared to the case where all transistors are set to low T ox, our approach achieves an average leakage reduction of 83% under 100nm models.

Original languageEnglish (US)
Pages (from-to)761-766
Number of pages6
JournalProceedings - Design Automation Conference
StatePublished - 2004
EventProceedings of the 41st Design Automation Conference - San Diego, CA, United States
Duration: Jun 7 2004Jun 11 2004


  • Dual T Circuits
  • Leakage power


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