@inproceedings{b85b786f3fd646909f9c5655fd6816bc,
title = "Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability",
abstract = "This paper develops a trace-based framework to enable concurrent process and FPGA architecture co-development. Based on process parameters and traces for FPGA applications, the framework calculates the chip level performance and power distribution and soft error rate (SER) with consideration of process variations and device aging. As examples to utilize the framework, the paper further applies heterogeneous gate lengths to logic and interconnects for energy reduction, and studies the interaction between device aging, process variation and SER.",
keywords = "FPGA architecture, FPGA power model",
author = "Lerong Cheng and Yan Lin and Lei He and Yu Cao",
year = "2008",
doi = "10.1145/1344671.1344696",
language = "English (US)",
isbn = "9781595939340",
series = "ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA",
pages = "159--168",
booktitle = "FPGA 2008 - Sixteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays",
note = "16th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2008 ; Conference date: 24-02-2008 Through 26-02-2008",
}