Abstract
This article makes the case for dynamic precision scaling to improve power efficiency by tailoring arithmetic precision adaptively to temporal changes in algorithmic noise tolerance throughout the execution.
| Original language | English (US) |
|---|---|
| Article number | 8430621 |
| Pages (from-to) | 30-39 |
| Number of pages | 10 |
| Journal | IEEE Micro |
| Volume | 38 |
| Issue number | 4 |
| DOIs | |
| State | Published - Jul 1 2018 |
Bibliographical note
Funding Information:This work was supported in part by NSF grant no. CCF-1438286.
Publisher Copyright:
© 1981-2012 IEEE.
Keywords
- dynamic precision scaling
- floating point arithmetic
- hardware
- precision reduction
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