Abstract
A timing optimization algorithm dealing with circuits containing mixed domino and static logic is described. Transistor-level node timing constraints of domino logic is described. The optimization procedure preserves the requirements of maintaining adequate noise margins by constraining the sizing procedure. After sizing, charge-sharing problems are identified with a new method and rectified.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 266-269 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 6 |
| State | Published - 1998 |
| Event | Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA Duration: May 31 1998 → Jun 3 1998 |