Timing optimization of mixed static and domino logic

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Abstract

A timing optimization algorithm dealing with circuits containing mixed domino and static logic is described. Transistor-level node timing constraints of domino logic is described. The optimization procedure preserves the requirements of maintaining adequate noise margins by constraining the sizing procedure. After sizing, charge-sharing problems are identified with a new method and rectified.

Original languageEnglish (US)
Pages (from-to)266-269
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume6
StatePublished - 1998
EventProceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
Duration: May 31 1998Jun 3 1998

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