TY - JOUR
T1 - Timing-driven partitioning for two-phase domino and mixed static/domino implementations
AU - Zhao, Min
AU - Sapatnekar, Sachin S.
PY - 1999
Y1 - 1999
N2 - Domino logic is a high-performance circuit configuration that is usually embedded in static logic environment and tightly coupled with the clocking scheme. In this paper, the timing-driven partitioning algorithms that partition a logic network between (1) static and domino implementations, and (2) the phases of a two-phase clock, are provided. In addition, an efficient static mapping algorithm is described.
AB - Domino logic is a high-performance circuit configuration that is usually embedded in static logic environment and tightly coupled with the clocking scheme. In this paper, the timing-driven partitioning algorithms that partition a logic network between (1) static and domino implementations, and (2) the phases of a two-phase clock, are provided. In addition, an efficient static mapping algorithm is described.
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M3 - Conference article
AN - SCOPUS:0033319556
SN - 1092-3152
SP - 107
EP - 110
JO - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
JF - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
T2 - Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design (ICCAD-99)
Y2 - 7 November 1999 through 11 November 1999
ER -