Abstract
Resistive-random-access-memory (ReRAM) based processing-in-memory (R2PIM) accelerators show promise in bridging the gap between Internet of Thing devices' constrained resources and Convolutional/Deep Neural Networks' (CNNs/DNNs') prohibitive energy cost. Specifically, R2PIM accelerators enhance energy efficiency by eliminating the cost of weight movements and improving the computational density through ReRAM's high density. However, the energy efficiency is still limited by the dominant energy cost of input and partial sum (Psum) movements and the cost of digital-to-analog (D/A) and analog-to-digital (AD) interfaces. In this work, we identify three energy-saving opportunities in R22PIM accelerators: analog data locality, time-domain interfacing, and input access reduction, and propose an innovative R2PIM accelerator called TIMELY, with three key contributions: (1) TIMELY adopts analog local buffers (ALBs) within ReRAM crossbars to greatly enhance the data locality, minimizing the energy overheads of both input and Psum movements; (2) TIMELY largely reduces the energy of each single D/A (and AD) conversion and the total number of conversions by using time-domain interfaces (TDIs) and the employed ALBs, respectively; (3) we develop an only-once input read O2IR) mapping method to further decrease the energy of input accesses and the number of D/A conversions. The evaluation with more than 10 CNN/DNN models and various chip configurations shows that, TIMELY outperforms the baseline R2PIM accelerator, PRIME, by one order of magnitude in energy efficiency while maintaining better computational density (up to 31.2×) and throughput (up to 736.6×). Furthermore, comprehensive studies are performed to evaluate the effectiveness of the proposed ALB, TDI, and O2IR in terms of energy savings and area reduction.
Original language | English (US) |
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Title of host publication | Proceedings - 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture, ISCA 2020 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 832-845 |
Number of pages | 14 |
ISBN (Electronic) | 9781728146614 |
DOIs | |
State | Published - May 2020 |
Externally published | Yes |
Event | 47th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2020 - Virtual, Online, Spain Duration: May 30 2020 → Jun 3 2020 |
Publication series
Name | Proceedings - International Symposium on Computer Architecture |
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Volume | 2020-May |
ISSN (Print) | 1063-6897 |
Conference
Conference | 47th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2020 |
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Country/Territory | Spain |
City | Virtual, Online |
Period | 5/30/20 → 6/3/20 |
Bibliographical note
Publisher Copyright:© 2020 IEEE.
Keywords
- Analog Processing
- Neural Networks
- Processing In Memory
- Resistive-Random-Access-Memory (Reram)