We present results on time borrowing in skew-tolerant domino logic circuits for a 32-bit adder, a 64-bit adder and a 32-bit pipelined multiplier. The adders are built using enhanced multiple output domino logic and the multiplier uses modified Booth encoding and a Wallace tree. We illustrate how the resulting soft clock edges allow advantageous time borrowing to occur in these functional units. In this way, limitations due to delay imbalances between stages are removed, allowing the circuits to operate at a higher speed.
|Original language||English (US)|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 2000|