Three-dimensional place and route for FPGAs

Cristinel Ababei; Hushrav Mogal; Kia Bazargan

doi:10.1145/1120725.1121015

Three-dimensional place and route for FPGAs

Cristinel Ababei, Hushrav Mogal, Kia Bazargan

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

26 Scopus citations

Abstract

We present timing-driven partitioning and simulated annealing based placement algorithms together with a detailed routing tool for 3D FPGA integration. The circuit is first divided into layers with limited number of inter-layer vias, and then placed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform to explore the potential benefits in terms of delay and wire-length that 3D technologies can offer for FPGA fabrics. Experimental results show on average a total decrease of 21% in wire-length and 24% in delay, can be achieved over traditional 2D chips, when five layers are used in 3D integration.

Original language	English (US)
Title of host publication	Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	773-778
Number of pages	6
ISBN (Print)	0780387368, 9780780387362
DOIs	https://doi.org/10.1145/1120725.1121015
State	Published - 2005
Event	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China Duration: Jan 18 2005 → Jan 21 2005

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2

Other

Other	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Country/Territory	China
City	Shanghai
Period	1/18/05 → 1/21/05

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10.1145/1120725.1121015

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Ababei, C., Mogal, H., & Bazargan, K. (2005). Three-dimensional place and route for FPGAs. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 (pp. 773-778). Article 1466456 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/1120725.1121015

Three-dimensional place and route for FPGAs. / Ababei, Cristinel; Mogal, Hushrav; Bazargan, Kia.
Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. Institute of Electrical and Electronics Engineers Inc., 2005. p. 773-778 1466456 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ababei, C, Mogal, H & Bazargan, K 2005, Three-dimensional place and route for FPGAs. in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005., 1466456, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2, Institute of Electrical and Electronics Engineers Inc., pp. 773-778, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 1/18/05. https://doi.org/10.1145/1120725.1121015

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AB - We present timing-driven partitioning and simulated annealing based placement algorithms together with a detailed routing tool for 3D FPGA integration. The circuit is first divided into layers with limited number of inter-layer vias, and then placed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform to explore the potential benefits in terms of delay and wire-length that 3D technologies can offer for FPGA fabrics. Experimental results show on average a total decrease of 21% in wire-length and 24% in delay, can be achieved over traditional 2D chips, when five layers are used in 3D integration.

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ER -

Three-dimensional place and route for FPGAs

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