Abstract
We present timing-driven partitioning and simulated-annealing (SA)-based placement algorithms together with a detailed routing tool for three-dimensional (3-D) field-programmable gate array (FPGA) integration. The circuit is first divided into layers with a limited number of interlayer vias, and then placed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform to explore the potential benefits, in terms of delay and wire length (WL), that 3-D technologies can offer for FPGA fabrics. Experimental results show, on average, a total decrease of 25% in WL and 35% in delay can be achieved over traditional two-dimensional chips, when ten layers are used in 3-D integration.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1132-1140 |
| Number of pages | 9 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 25 |
| Issue number | 6 |
| DOIs | |
| State | Published - Jun 2006 |
Bibliographical note
Funding Information:Manuscript received June 28, 2004; revised November 28, 2004. This paper was supported in part by the Office of the Vice President for Research and Dean of the Graduate School of the University of Minnesota under Grant 1546-522-5980. This paper was recommended by Associate Editor M. D. F. Wong.
Keywords
- Field-programmable gate arrays (FPGAs)
- Routing
- Three-dimensional (3-D) circuits
- Timing-driven placement