We present timing-driven partitioning and simulated-annealing (SA)-based placement algorithms together with a detailed routing tool for three-dimensional (3-D) field-programmable gate array (FPGA) integration. The circuit is first divided into layers with a limited number of interlayer vias, and then placed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform to explore the potential benefits, in terms of delay and wire length (WL), that 3-D technologies can offer for FPGA fabrics. Experimental results show, on average, a total decrease of 25% in WL and 35% in delay can be achieved over traditional two-dimensional chips, when ten layers are used in 3-D integration.
|Original language||English (US)|
|Number of pages||9|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - Jun 1 2006|
- Field-programmable gate arrays (FPGAs)
- Three-dimensional (3-D) circuits
- Timing-driven placement