Thermal via placement in 3D ICs

Brent Goplen, Sachin Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

146 Scopus citations

Abstract

As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promising way of mitigating thermal issues by lowering the thermal resistance of the chip itself. However, thermal vias take up valuable routing space, and therefore, algorithms are needed to minimize their usage while placing them in areas where they would make the greatest impact. With the developing technology of three-dimensional integrated circuits (3D ICs), thermal problems are expected to be more prominent, and thermal vias can have a larger impact on them than in traditional 2D ICs. In this paper, thermal vias are assigned to specific areas of a 3D IC and used to adjust their effective thermal conductivities. The thermal via placement method makes iterative adjustments to these thermal conductivities in order to achieve a desired maximum temperature objective. Finite element analysis (FEA) is used in formulating the method and in calculating temperatures quickly during each iteration. As a result, the method efficiently achieves its thermal objective while minimizing the thermal via utilization.

Original languageEnglish (US)
Title of host publicationProceedings of ISPD'05 - 2005 International Symposium on Physical Design
Pages167-174
Number of pages8
StatePublished - Dec 27 2005
Event2005 International Symposium on Physical Design, ISPD'05 - San Francisco, CA, United States
Duration: Apr 3 2005Apr 6 2005

Other

Other2005 International Symposium on Physical Design, ISPD'05
CountryUnited States
CitySan Francisco, CA
Period4/3/054/6/05

Keywords

  • 3-D IC
  • 3-D VLSI
  • Finite element analysis
  • Placement
  • Routing
  • Temperature
  • Thermal gradient
  • Thermal optimization
  • Thermal via

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