Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks

Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Computationally expensive temperature and power grid analyses are required during the design cycle to guide IC design. This paper employs encoder-decoder based generative (EDGe) networks to map these analyses to fast and accurate image-to-image and sequence-to-sequence translation tasks. The network takes a power map as input and outputs the temperature or IR drop map. We propose two networks: (i) ThermEDGe: a static and dynamic full-chip temperature estimator and (ii) IREDGe: a full-chip static IR drop predictor based on input power, power grid distribution, and power pad distribution patterns. The models are design-independent and must be trained just once for a particular technology and packaging solution. ThermEDGe and IREDGe are demonstrated to rapidly predict on-chip temperature and IR drop contours in milliseconds (in contrast with commercial tools that require several hours or more) and provide an average error of 0.6% and 0.008% respectively.

Original languageEnglish (US)
Title of host publicationProceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages690-696
Number of pages7
ISBN (Electronic)9781450379991
DOIs
StatePublished - Jan 18 2021
Event26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 - Virtual, Online, Japan
Duration: Jan 18 2021Jan 21 2021

Publication series

NameProceedings of the 26th Asia and South Pacific Design Automation Conference

Conference

Conference26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
Country/TerritoryJapan
CityVirtual, Online
Period1/18/211/21/21

Bibliographical note

Publisher Copyright:
© 2021 Association for Computing Machinery.

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