This paper presents a novel approach for theoretical estimation of power consumption in digital binary adders. Closed-form expressions for power consumption of four different types of binary adders - the ripple-carry adder, the Manchester adder, a multiplexor-based carry-select adder and an efficient tree-based look-ahead adder - are derived in terms of word-length and pre-computed technology-specific energy parameters. These expressions are verified to be accurate to within 1-5% by simulation using the HEAT tool.
|Original language||English (US)|
|Number of pages||5|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - Jan 1 1998|
|Event||Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA|
Duration: May 31 1998 → Jun 3 1998