Theoretical analysis of word-level switching activity in the presence of glitching and correlation

Janardhan H. Satyanarayana, Keshab K. Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

This paper presents a novel analytical approach to compute the switching activity in digital circuits at the word-level in the presence of glitching and correlation. The proposed approach makes use of signal statistics such as mean, variance, and autocorrelation. A novel expression is derived for the switching activity αf at the output node f of an arbitrary circuit in terms of time-slot autocorrelation coefficient, the expected value, and the signal probability. The switching activity analysis of a signal at the word-level is computed by summing the activities of all the individual bits constituting the signal. A novel relationship between the correlation coefficient of the higher order bits of a normally distributed signal and the bit where the correlation begins is also presented. The proposed approach can estimate the switching activity in less than a second which is order of magnitude faster than simulation based approaches. Simulation results show that the errors using the proposed approach are about 6% on an average and that the approach is well suited even for highly correlated speech and music signals.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE Great Lakes Symposium on VLSI
PublisherIEEE
Pages46-49
Number of pages4
ISBN (Print)0769501044
StatePublished - Dec 1 1999
EventProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA
Duration: Mar 4 1999Mar 6 1999

Publication series

NameProceedings of the IEEE Great Lakes Symposium on VLSI
ISSN (Print)1066-1395

Other

OtherProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
CityAnn Arbor, MI, USA
Period3/4/993/6/99

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