Theoretical analysis of word-level switching activity in the presence of glitching and correlation

Janardhan H. Satyanarayana, Keshab K. Parhi

Research output: Contribution to journalArticle

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Abstract

A method to compute the switching activity in digital circuits at the word level in the presence of glitching and correlation is proposed. The method uses signal statistics such as a mean, variance, and autocorrelation. It is shown that the switching activity at the output node of any arbitrary circuit in the presence of glitching and correlation at the word level is computes by summing the activities of all the individual bits constituting the signal. The method can estimate the switching activity in less than a second which is orders of magnitude faster than simulation-based approaches.

Original languageEnglish (US)
Pages (from-to)148-159
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume8
Issue number2
DOIs
StatePublished - Jan 1 2000

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