The recursive NanoBox processor grid: A reliable system architecture for unreliable nanotechnology devices

A. J. KleinOsowski, Kevin KleinOsowski, Vijay Rangarajan, Priyadarshini Ranganath, David J Lilja

Research output: Contribution to conferencePaperpeer-review

12 Scopus citations

Abstract

Advanced molecular nanotechnology devices are expected to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS devices. We introduce the Recursive NanoBox Processor Grid as an application specific, fault-tolerant, parallel computing system designed for fabrication with unreliable nanotechnology devices. In this initial study we construct VHDL models of the NanoBox Processor cell ALU and evaluate the effectiveness of our recursive fault masking approach in the presence of random transient errors. Our analysis shows that the ALU can calculate correctly 100 percent of the time with raw FIT (failures in time) rates as high as 10 23. We achieve this error correction with an area overhead on the order of 9x, which is quite reasonable given the high integration densities expected with nanodevices.

Original languageEnglish (US)
Pages167-176
Number of pages10
StatePublished - Oct 1 2004
Event2004 International Conference on Dependable Systems and Networks - Florence, Italy
Duration: Jun 28 2004Jul 1 2004

Other

Other2004 International Conference on Dependable Systems and Networks
CountryItaly
CityFlorence
Period6/28/047/1/04

Keywords

  • Architecture
  • Fault-injection
  • Fault-masking
  • Nanotechnology
  • VLSI

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