The impact of shallow trench isolation effects on circuit performance

Sravan K. Marella, Sachin S. Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

In nanometer technologies, shallow trench isolation (STI) induces thermal residual stress in active silicon due to post-manufacturing thermal mismatch. The amount of STI around an active region depends on the layout of the design, and the biaxial stress due to STI results in placement-dependent variations in the the transistor mobilities and threshold voltages of the active devices. An analytical model based on inclusion theory in micromechanics is employed to accurately estimate the stresses and the strains induced in the active region by the surrounding STI in the layout. The induced changes in mobility and threshold voltage changes are computed at the transistor level, and then propagated to the gate and circuit levels to predict circuit-level delay and leakage power for a given placement.

Original languageEnglish (US)
Title of host publication2013 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2013 - Digest of Technical Papers
Pages289-294
Number of pages6
DOIs
StatePublished - Dec 1 2013
Event2013 32nd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2013 - San Jose, CA, United States
Duration: Nov 18 2013Nov 21 2013

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Other

Other2013 32nd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2013
Country/TerritoryUnited States
CitySan Jose, CA
Period11/18/1311/21/13

Keywords

  • Analytical Model
  • Inclusion Theory
  • Shallow Trench Isolation
  • Static Timing Analysis

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