The impact of BTI variations on timing in digital logic circuits

Jianxin Fang, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

31 Scopus citations

Abstract

A new framework for analyzing the impact of bias temperature instability (BTI) variations on timing in large-scale digital logic circuits is proposed in this paper. This approach incorporates both the reaction-diffusion model and the charge-trapping model for BTI and embeds these into a temporal statistical static timing analysis framework capturing process variations and path correlations. Experimental results on 32-, 22-, and 16-nm technology models, which were verified through Monte Carlo simulation, confirm that the proposed approach is fast, accurate, and scalable and indicate that BTI variations make a significant contribution to circuit-level timing variations.

Original languageEnglish (US)
Article number6407977
Pages (from-to)277-286
Number of pages10
JournalIEEE Transactions on Device and Materials Reliability
Volume13
Issue number1
DOIs
StatePublished - 2013

Keywords

  • Bias temperature instability (BTI)
  • circuit reliability
  • process variation (PV)
  • timing analysis

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