TY - JOUR
T1 - The impact of BTI variations on timing in digital logic circuits
AU - Fang, Jianxin
AU - Sapatnekar, Sachin S.
PY - 2013
Y1 - 2013
N2 - A new framework for analyzing the impact of bias temperature instability (BTI) variations on timing in large-scale digital logic circuits is proposed in this paper. This approach incorporates both the reaction-diffusion model and the charge-trapping model for BTI and embeds these into a temporal statistical static timing analysis framework capturing process variations and path correlations. Experimental results on 32-, 22-, and 16-nm technology models, which were verified through Monte Carlo simulation, confirm that the proposed approach is fast, accurate, and scalable and indicate that BTI variations make a significant contribution to circuit-level timing variations.
AB - A new framework for analyzing the impact of bias temperature instability (BTI) variations on timing in large-scale digital logic circuits is proposed in this paper. This approach incorporates both the reaction-diffusion model and the charge-trapping model for BTI and embeds these into a temporal statistical static timing analysis framework capturing process variations and path correlations. Experimental results on 32-, 22-, and 16-nm technology models, which were verified through Monte Carlo simulation, confirm that the proposed approach is fast, accurate, and scalable and indicate that BTI variations make a significant contribution to circuit-level timing variations.
KW - Bias temperature instability (BTI)
KW - circuit reliability
KW - process variation (PV)
KW - timing analysis
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U2 - 10.1109/TDMR.2013.2237910
DO - 10.1109/TDMR.2013.2237910
M3 - Article
AN - SCOPUS:84874978609
SN - 1530-4388
VL - 13
SP - 277
EP - 286
JO - IEEE Transactions on Device and Materials Reliability
JF - IEEE Transactions on Device and Materials Reliability
IS - 1
M1 - 6407977
ER -