The effect of using state-based priority information in a shared-memory multiprocessor cache replacement policy

Farnaz Mounes-Toussi, David J. Lilja

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

The cache replacement policy is one of the factors that determines the effectiveness of cache memories. We study the impact of incorporating the cache block coherence state information in the random replacement policy in a shared memory multiprocessor. We assign replacement priority to each cache block within a set based on its state. To reduce the probability of replacing a recently accessed block and to adapt to the program's access patterns, we also associate with each set an MRU (Most Recently Used) state. The MRU state causes the lowest replacement priority to be assigned to the blocks in the same state as the MRU state. Our evaluations indicate that, with the appropriate priority assignment and a set associativity size less than 16, the proposed policy can outperform the Random and Random & Invalid policies and, in some cases, can even outperform the LRU policy.

Original languageEnglish (US)
Title of host publicationProceedings - 1998 International Conference on Parallel Processing, ICPP 1998
EditorsTen H. Lai
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages217-224
Number of pages8
ISBN (Electronic)0818686502
DOIs
StatePublished - Jan 1 1998
Event1998 International Conference on Parallel Processing, ICPP 1998 - Minneapolis, United States
Duration: Aug 10 1998Aug 14 1998

Publication series

NameProceedings of the International Conference on Parallel Processing
ISSN (Print)0190-3918

Other

Other1998 International Conference on Parallel Processing, ICPP 1998
CountryUnited States
CityMinneapolis
Period8/10/988/14/98

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    Mounes-Toussi, F., & Lilja, D. J. (1998). The effect of using state-based priority information in a shared-memory multiprocessor cache replacement policy. In T. H. Lai (Ed.), Proceedings - 1998 International Conference on Parallel Processing, ICPP 1998 (pp. 217-224). (Proceedings of the International Conference on Parallel Processing). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICPP.1998.708489